1. Field of the Invention
The present invention relates to an energy beam exposure method and an exposure apparatus for use in manufacture of a semiconductor device.
2. Description of the Related Art
Recently, as large scale integrated circuits (LSI) are becoming higher in density, electron beam exposure (EB exposure) is actually used. One type of EB exposure is character projection exposure (CP exposure) which is a kind of partial batch exposure. In this system (CP system), from an aperture mask (CP aperture mask) having plural character projection patterns (CP patterns), a desired CP pattern is selected, and the electron beam having passed through this selected CP pattern is reduced to a desired size of the sample and emitted.
However, the conventional CP exposure method involves the following problems. In the case of beam adjustment before exposure of an electron beam exposure apparatus using a general rotation symmetrical lens, astigmatism adjustment is done. The astigmatism adjustment is done such that the beam blurs in the X- and Y-directions may be identical. On the other hand, as shown in FIG. 27, when different beam blurs are set in the X- and Y-directions, the resolution in a specific direction can be enhanced.
Recently, a charged beam exposure apparatus using a multiple-pole lens designed to pass through different projectories is being researched. When using a multiple-pole lens, since the beam trajectories in the X- and Y-directions are different, there is no beam blur crossover (beam converging point). The advantage is that the beam blur can be reduced, but the beam blur differs in the X- and Y-directions on principle. In such a case, therefore, the CP pattern cannot be correctly transferred onto the sample by the conventional CP exposure.
More recently, effectiveness of a method of forming the wiring in a 45-degree or 135-degree direction is confirmed. That is, as compared with the conventional wiring connected in the vertical or horizontal direction, oblique wiring can enhance the operating speed of the semiconductor device by wiring the elements straightly.
However, considering oblique wiring by the conventional exposure technology, the following problems are present.
First, to form an oblique CP pattern corresponding to the oblique wiring, as shown in FIG. 28A and FIG. 28B, it is required to form an opening 200 inclined to the X- or Y-direction on the aperture mask. The opening 200 in FIG. 28A shows one rectangular opening inclined obliquely, and the opening 200 in FIG. 28B shows an opening obtained by forming plural square openings in an oblique direction. The problem is that the obliquely inclined opening 200 of this kind is hard to manufacture as compared with the opening parallel to the X- or Y-direction.
Further, using triangular or square CP pattern, when forming an oblique shot pattern (exposure pattern) by linking the triangular or square beams 201 in an oblique direction as shown in FIG. 29A and FIG. 29B, the number of beam shots increases and the exposure time becomes longer. It means a longer manufacturing time is needed in LSI manufacture.
Alternatively, in the case of oblique wiring by using variable shaping beam (VSB), if the beam blur differs in the X- and Y-direction, the pattern dimension may differ. That is, in the case of oblique wiring by using an exposure apparatus different in the beam blurs in the X- and Y-directions, it is hard to transfer the oblique wiring pattern with high precision.
In the EB exposure, the region to be exposed is divided into plural beam deflection regions, and is exposed. Herein, the maximum beam size is only several μm square, and the pattern to be exposed must be divided into shots of several μm square. Accordingly, when exposing a pattern larger than the maximum beam size, this large pattern is formed by plural shot patterns, and shot linking (shot junction) occurs.
In the conventional electron beam exposure apparatus different in the beam blurs in the X- and Y-directions, there is a position deviation of several nanometers or tens of nanometers respectively among shot positions and among fields. Therefore, as the pattern becomes finer, the effect of difference of beam blurs in the X- and Y-directions becomes larger. As a result, patterns to be linked in design may not be actually linked, or patterns not to be linked in design are actually linked, and pattern defects occur. Specifically, problems of open defect and short defect of wiring are likely to occur. It also leads to decline of reliability of device and drop of yield.
In manufacture of LSIs, uniformity of dimensions within wafer is important. In the recent finer pattern trend, the demand for dimensional precision is becoming severer. One of the causes of dimensional variation of pattern is a local fluctuation of pattern size occurring at the time of etching. This phenomenon is explained by referring to FIG. 30A and FIG. 30B.
In FIG. 30A and FIG. 30B, reference numeral 300 is a substrate, 301 is a film to be processed, 302 is a resist pattern, and 302a and 302b are resist pattern blocks. As shown in FIG. 30B, the spacing is wide between the resist pattern blocks 302a and 302b. 
When the film 301 is etched in this state, as shown in FIG. 30B, the size of the etching pattern 301a of the film at the right end of the resist pattern block 302a increases. Similarly, the size of the etching pattern 301b of the film at the left end of the resist pattern block 302b increases. That is, the pattern size of the film 310 increases at the lower side of the pattern covering rate, which is a local dimensional variation.
As a measure against such local dimensional variation, the pattern dimension at the location of dimensional variation may be corrected at the stage of the design data.
When such a method is employed, however, new problems occur as follows.
The dimensional variation amount of an etching pattern depends on the etching condition. Therefore, every time the etching condition is changed, the design data must be corrected. In this case, it is needed to remake the drawing data in the EB exposure. Or, in the case of partial batch exposure (CP exposure) or batch transfer exposure, it is necessary to remake the aperture mask such as a partial batch mask (CP mask) or transfer mask. It leads to other problems, such as a longer time required in exposure process, a longer manufacturing period in the LSI manufacture, and a higher manufacturing cost.
Besides, the electron beam exposure apparatus of the conventional CP system has the following problem. The beam blur increases in proportion to the beam current as shown in formula (1).Blur=(I·L)/(α·V1.5)  (1)where I is a beam current, L is an optical path length (distance from an electron gun to a wafer), α is an opening angle, and V is an acceleration voltage.
Accordingly, the beam blur of the L/S pattern larger in the total beam current is larger than that of an independent pattern smaller in the total beam current, and the resolution deteriorates.